Current regulating arrangement for coincidence memories



Nov. 3, 1964 B. s. MAGNUSSON CURRENT REGULATING ARRANGEMENT FOR COINCIDENCE MEMORIES Filed May 15. 1961 2 Sheets-Sheet 1 1964 B. G. MAGNUSSON 3,1 ,8

CURRENT REGULA'I ING ARRANGEMENT FOR COINCIDENCE MEMORIES Filed May 15, 1961 2 Sheets-Shed 2 fs b ig 'sfi-fi b bfl fa b 71- roR/ves United States Patent 3,155,842 CURRENT REGULATING ARRANGEMENT FOR COINCIDENCE MEMCRIES Bengt Gunnar Magnusson, Enskede, Sweden, assignor to Telefonalrtieholaget L M Ericsson, Stockholm, Sweden,

a corporation of Sweden Filed May 15, 1961, Ser. No. 110,152? Claims priority, application Sweden, May 24, 1960 1 Claim. (Cl. 307-885) in coincidence memories in electronic data machines certain demands must be made upon the so called reading and writing currents or co-ordinate currents, which are transmitted through memory elements of the memories, for instance ferrite cores. Among these demands there may be mentioned a reproduceable shape of a curve, which as far as possible is independent of the information unit of the memory and has the most possible constant amplitude during reading and writing respectively. Further the loss effects must be held at a reasonable level as for instance it is possible to make essential savings with a reduced current consumption in automatic telephone exchanges.

The reading and writing currents must have a reproduceable shape of a curve independent of the information unit of the memory, for instance, so that the cores of the memory, which shall give signals at the same time, really do so at exactly the same time. An amplitude of the reading and writing currents independent of the actual load is required for instance, in order to eliminate the disturbing voltages emitted by ferrite cores. In order to have the current values suitably adjusted to the temperature qualities of the ferrite cores, the currents should be compensated With respect to temperature.

The present invention relates to an arrangement for regulation and stabilization of the reading and writing currents in a coincidence memory in an electronic data machine, such as en electronic automatic telephone exchange.

The invention is mainly characterized by a chopper arrangement, consisting of a comparator with two comparison elements connected in a comparison circuit, for instance transistors, a connecting circuit built of logical circuit elements and at least two switch elements, one of which, for instance a transistor, is connected to a higher potential, and one of which, for instance a diode, is connected to a lower potential. Said comparator is arranged to test current flowing through the inductance elements of the integration circuit and, if its level during the intervals between the reading and writing phases is too low, temporarily and automatically raise the voltage across the inductance element by connecting said switch element connected to a higher potential to the inductance element, whereby the current flowing through the inductance element is restored to its original level, but otherwise connect said switch element connected to the lower potential to the inductance element of the integration circuit.

One embodiment of the arrangment according to the invention will be described below in connection with the figures, of which FIG. 1 shows a diagram of a circuit system according to the invention, and

FIG. 2 shows an example of a time diagram for the system according to FIG. 1 in combination with a coincidence memory.

In FIG. 1, A and B indicate driving pulse amplifiers of a type known per se, which supply current to all the X- and/or Y-co-ordinate lines of a memory matrix via a connecting arrangement. The connecting arrangement C comprises, for instance a transformer T through the primary winding of which the currents supplied by the "ice driving pulse amplifiers A and B pass. All the X- and/ or Y-co-ordinate lines are connected to the secondary side of the transformer T which lines pass the memory element of the memory matrix, which is supposed to consist of ferrite cores in the embodiment. of the transformer connection a rapid action is achieved at the same time as the number of necessary feeding voltages can be kept low. Further, the arrangment in FIG. 1 comprises a chopper arrangement consisting of two switch elements Q, for instance a transistor, and D, for instance a rectifier and of a comparator E and a connecting circuit F. Finally, the arrangement also includes an integration circuit, which consists of an inductance L a resistance R and optionally a capacitance C An example of a time diagram for a coincidence memory combined with an arrangement according to FIG. 1 is shown in FIG. 2. The diagram comprises a so called memory cycle, the duration of which is for instance of the magnitude of some micro-seconds. The memory cycle is supposed to be divided into 12 time intervals of the same length indicated To-Tg, TA and 1 The interval 1- -7 is a so called reading phase 'r during which the contents of the memory can be read, while 1- -7 is a so called writing phase 1 during which the writing of information in the memory can take place. FIG. 2 shows the shape of the curve an the size of the co-ordinate currents z' and i through the X- and Y- co-ordinate lines and also the size of the voltages 11 u and u in relation to ground at the points L, P and S respectively in the connecting arrangement C in FIG. 1.

The arrangement in FIG. 1 operates as follows: When information is to be read from or written into the memory, the-driving pulse amplifier A and the driving pulse amplifier B respectively supply current pulses i;, and i to the connecting arrangement C in a way which will be described below. In the secondary winding of the transformerT said co-ordinate currents i and i are then induced. These semi-currents form the semi-currents, which are transmitted through the ferrite cores of the memory matrix in the xand y-line respectively, and form the said reading and writing currents respectively. To enable these currents to satisfy the demands mentioned in the introduction, the current .pulse i and i are regulated to exact values by means of for instance the integration circuit L C R The regulation is achieved by providing that a constant mean current I is constantly flowing through the inductance element L, of the integration circuit. During the reading of the memory the current I consists of the current pulse i and during the Writing of information in the memory it consists of the current pulse i During short time intervals, when neither reading nor writing of information occurs in the memory, the current 1 consists of a current, which develops when the energy stored in the inductance L is discharged whereby the discharging current path consists for instance, of the rectifier D, the inductance L and the resistance R During long intervals between the reading and writing phases, when the energy stored in the inductance L is not sufficient to maintain the current I at a desired level, the transistor Q is connected to the inductance by aid of the comparator E and the connecting circuit F so often that the current I is kept substantially constant through the inductance, by temporarily raisingthe potential u at one terminal point of the inductance with each connection of the transistor Q. Consequently, the current I will be equal to the stationary top value of the reading and writing pulses i and i and the current I is determined by the mean voltage between the point X and ground divided by the total series resistance through the integration circuit between these two points. The feeding voltages for the arrangement in FIG. 1 are sym By making use L bolized by E, E and E and for them E E 0 (ground) E is valid.

During each so called reading phase T in FIG. 2, reading of the memory can take place, and therefore a voltage is applied during this phase to one of the inlets of an and circuit 0 connected to the driving pulse amplifier A in FIG. 1, for instance from a clock-generator. Whether reading really shall be effected or not during a certain reading phase is then determined, or if there is a reading pulse L or not at the second inlet of the and circuit 0 at the same time. If such be the case, a signal is obtained on the outlet of the and circuit 0 at which the driving pulse amplifier A, which in a known way consists of, for instance, a transistor Q and a transformer T supplies a current pulse z' to the connecting arrangement C via a diode D The reading pulse L can for instance appear from a special information memory or something like that.

Another and circuit 0 is similarly connected to the driving pulse amplifier B. The and circuit voltage from for instance a clock-generator is connected to one inlet of the and circuit during every writing phase r in FIG. 2. When the writing of information in the memory shall take place, a voltage is connected to the second inlet of the and circuit 0 at the same time in form of a writing pulse S. In doing so a signal is obtained at the outlet of the and circuit 0 The driving pulse amplifier B, which in a known way includes, for instance, a transistor Q and a transformer T supplies a current pulse i to the connecting arrangement C via a diode D The current pulses i and i from the driving pulse amplifiers A and B respectively pass the primary winding of the transformer T in the connecting arrangement C in opposite phase, and in the secondary winding said coordinate currents i and i are induced.

When for instance reading of the memory occurs, the driving pulse amplifier A supplies a current pulse i according to what is mentioned above, which current pulse passes via the connecting arrangement C to the integration circuit L C R The primary Winding of the transformer T in the connecting arrangement C is provided with a center tap, at which each winding half is connected parallel to a resistance R and a capacitance C Two parallel resonance circuits L C R are thus obtained, where L represents the total inductance value on to the primary side of the transformer T for semi-currents of the ferrite cores connected to the secondary side. When the current pulse i which in the best case will be a square wave, passes the parallel resonance circuit L C R the current edges will be mainly aperiodically damped. In this way the parallel resonance circuit L C R will consequently control the rise time of the current pulse i (i and the overshoots, if any.

The amplitude of the current pulse i and also i (i are determined by the integration circuit L C R The amplitude determination is made possible by having a current I with mainly the amplitude that is desired for the current pulse i permanently flowing through the inductance L When the reading conditions are satisfied and the driving pulse amplifier A is connected to the connecting arrangement C, the current pulse i;, will block the diode D and the current I will consist of the current pulse i Owing to the inertia of the integration circuit L C R and in particular the inertia of the inductance L a sudden change of the current 1 cannot occur, but instead the integration circuit will constitute a current holding arrangement, which means that the current pulse i will maintain the amplitude I During writing of information into the memory, the driving pulse amplifier B will, as mentioned above, supply a current pulse i (i in opposite direction in relation to the reading phase, the amplitude, the rise time and overshoot of which are determined in the same way as for corresponding magnitudes of the current pulse during the reading phase.

Even during the intervals which arise in the memory cycle between the reading and writing phases, and when none of the driving pulse amplifiers A and B are connected to the connecting arrangement C, a current I will permanently flow through the inductance L During such short intervals, for instance, the time interval T -T in FIG. 2, which have a duration of the magnitude of one microsecond, the current I can be maintained by discharging the energy which is stored in the inductance L through a current path, in which are included the diode D, which is connected to a potential lower than E for instance, ground, the inductance L and the resistance R If the inductance L and the resistance R are dime11- sioned in a suitable way, for example, a sutliciently long time constant in relation to the length of the time interval, the energy discharge will be limited to a value such that the current I will not decrease appreciably below the desired level.

With long intervals between the reading and writing phases in the memory cycle, the integration circuit L C R will have time to be discharged so much that the current I would decrease considerably towards the value 0, if no special steps are taken. According to the present invention the current I is kept at the original level by temporarily and automatically raising the potential at one terminal point X in FIG. 1 over the ground potential when the current I has decreased below a certain value determined in advance, at which the current reverts to the original level. The potential raise in the point X occurs automatically by aid of the comparator E, the connecting circuit F and the switch element Q, which latter comprises one transistor in the shown example of embodimerit.

The comparator E consists of two comparison elements, for instance, transistors Q and Q arranged in a comparison circuit. The base electrode of the transistor Q receives its control voltage over the resistance R which voltage is consequently determined by the current I Further the transistor Q receives its control voltage over a reference element, for instance a diode. In the shown embodiment a zener-diode D is connected to a potential divider determining the bias of the transistor Q, in which besides the reference element D the resistances R and R are included, whereby said bias is stabilized.

The control voltages are equally adjusted at the two transistors Q and Q4, at which the current through the common emitter resistances R of the two transistors is so divided that equally large parts of the current pass through each transistor. If the current I through the inductance L decreases, the action of the base electrode of the transistor Q will decrease, whereupon a small part of the current through the emitter resistance R passes through the transistor Q Hereby a small voltage drop is obtained across the collector resistance R of this transistor, and the voltage on the collector electrode of the transistor decreases to a more negative value. This voltage decrease is supplied to the connecting circuit F via a conductor J.

The connecting circuit F includes a number of logical circuit elements, known per se, for instance, two and circuits one or circuit one inverting circuit one and circuit, with for instance five inlets together, symbolized in FIG. 1 by TL, L, 1 S and J, and one outlet symbolized by K.

A raise of the potential in the point X will occur only during the long time intervals, for instance, 1 -1 in FIG. 2, or between two memory cycles which are far from each other in time, when neither the reading nor the Writing conditions are present, and when the energy stored in the inductance L is not sufiicient to maintain the current I at the original level. A potential raise during only these time intervals is achieved by providing the inlets of the connecting circuit F with the specific conditions for said time interval. Two inlets of the connecting circuit are supplied with the pulses TL and T supplied by the clock-generator during the reading and writing phases respectively, while two of the other inlets are supplied with the reading and writing pulses L and S respectively supplied by, for instance, a special instruction memory. These four dillerent pulses are consequently the same that are supplied to the and circuits O and 0 at the driving pulse amplifiers A and B respectively. The fifth inlet of the connecting circuit F is supplied with the possible voltage decrease in the comparator E via the conductor J. By suitable connection of said logical circuit elements included in the connecting circuit F a signal can be obtained at the outlet K of the connecting circuit F only when the atore-stated conditions are present. The potential in the point X shall be increased only when the current 1 has decreased below a value determined in advance, that is, when the comparator E supplies a sufficiently negative voltage to the conductor J, and at the same time neither the driving pulse amplifier A nor the driving pulse amplifier B feeds current to the connecting circuit C, The specific conditions on the inlets of the connecting circuit F will then be with circuit logical expressions that 1' shall be equal to 1 but TL and L may not be 1 at the same time, and neither may 73 and S be 1 at the same time. When these conditions are present an outlet voltage on the outlet K of the connecting circuit is obtained. This voltage is supplied to the base electrode of the transistor Q via a transformer T and makes the transistor conductive. The voltage decrease across a conductive transistor is low, and therefore, when the transistor Q is conductive, the potential in the point X will rise to a value near the emitter potential of the transistor Q. When the current I has reverted to its original value the voltage, which is passed to the conductor I from the comparator E, disappears. The condition 1:1 is no longer present for the connecting circuit F and therefore the voltage at its outlet K disappears and the transistor Q is blocked. If the remaining conditions are maintained at the inlets of the connecting circuit F, the cycle is repeated as soon as the condition J=1 appears again, that is, when the current I has decreased again below the original value. If the sensitivity of the comparator E is made sufficiently high, the difference between the two limit values on I can be lower than, for instance, 1%, that is, 1 is practically constant.

The arrangement according to the invention can advantageously be provided with an arrangement for temperature compensation of the current 1 flowing through the inductance L At an increased temperature of the surroundings the co-ordinate currents i and i through the ferrite cores of the memory matrix will be smaller,

whereby also the current 1 which according to the above mentioned determines the amplitude of the co-ordinate currents i and i shall be lower. Said temperature compensation is achieved by, for instance, using a diode as reference element D suitably a silicone diode, with the same temperature dependence as the ferrite cores in the memory matrix. At an increased temperature the control voltage of the transistor Q, will decrease somewhat and the current 1 through the inductance element L will be adjusted to a somewhat lower value, so that the transistor Q will have the same control voltage as the transistor Q 1 claim:

A current-regulating circuit system for electronic dataprocessing apparatus, said circuit system comprising an inductance means, a comparison circuit having an input and an output, a connecting network, a first switch means having a control terminal, and a second switch means, one terminal of said inductance means being connected to said switch means and the other terminal to the input of said comparison circuit, the output side of the comparison circuit being connected to the input of the connecting network, said first switch means being connected to a first potential, and the control terminal of said first switch means being connected to the output side of said connecting network, the second switch means being connected to a second potential lower than said first potential, said inductance means and said switch means having a common circuit point, and a source of current connected to said common point for supplying write-in and read-out current thereto at spaced intervals of time, said comparison circuit being controlled by the flow of current through said inductance means and in response to a flow of current below a predetermined level through said inductance means during periods of time of no-current supply from said source of current controlling said first switch means to connect said first potential to said common point, thereby to raise the potential through the inductance means during said periods of time, and controlling said second switch means in periods of current flow from the source of current to connect said second potential to said common point.

References Cited in the file of this patent UNITED STATES PATENTS 2,964,655 Mann Dec. 13, 1960 3,012,153 Mussard Dec. 5, 1961 3,013,159 Sautels Dec. 12, 1961 FOREIGN PATENTS 577,117 Canada June 2, 1959 

